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HANBit
HAN BIT
HMS12832M4
SRAM MODULE 512KByte (128K x 32-Bit) Part No.
HMS12832M4
GENERAL DESCRIPTION
The HMS12832M4 is a high-speed static random access memory (SRAM) module containing 131,072 words organized in a x32-bit configuration. The module consists of four 128K x 8 SRAMs mounted on a 64-pin, singlesided, FR4-printed circuit board. PD0 and PD1 identify the module's density allowing interchangeable use of alternate density, industry- standard modules. Four chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module's 4 bytes independently. Output enable(/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
PIN ASSIGNMENT FEATURES
Access times : 12, 15 and 20ns High-density 512KByte design High-reliability, high-speed design Single + 5V 0.5V power supply Easy memory expansion with /CE and /OE functions All inputs and outputs are TTL-compatible Industry-standard pinout FR4-PCB design
Vss PD0 PD1 DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 1 2 3 4 5 6 7 8 9 /CE4 33 /CE3 34 NC 35 A16 36 /OE 37 Vss 38 DQ24 39 DQ16 40 DQ25 41 DQ17 42 DQ26 43 DQ18 44 DQ27 45 DQ19 46 A3 47 A10 48 A4 49 A11 50 A5 51 A12 52 Vcc 53 A13 54 A6 55 DQ20 56 DQ28 57 DQ21 58 DQ29 59 DQ22 60 DQ30 61 DQ23 62 DQ31 63 Vss 64
DQ3 10 DQ11 11 Vcc 12 A0 13 A7 14 A1 15 A8 16 A2 17 A9 18 DQ12 19 DQ4 20 DQ13 21
OPTIONS
Timing
8ns access 10ns access 12ns access 15ns access 20ns access
MARKING
-8 -10 -12 -15 -20 M
DQ5 22 DQ14 23 DQ6 24 DQ15 25 DQ7 26 Vss 27 /WE 28 A15 29 A14 30 /CE2 31 /CE1 32
Packages
64-pin SIMM
SIMM TOP VIEW
PD0 = Open PD1 = Open
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HANBit FUNCTIONAL BLOCK DIAGRAM
32 DQ0 - DQ31 A0 - A16 17 A0-16 DQ 0-7 /WE /OE
HMS12832M4
U1
/CE
/CE1 A0-16 DQ 8-15 /WE /OE
U2
/CE
/CE2 A0-16 DQ16-23 /WE /OE
U3
/CE
/CE3 A0-16 DQ24-31 /WE /OE /WE /OE
U4
/CE PRESENCE-DETECT PD0 = Open PD1 = Open
/CE4
TRUTH TABLE
MODE STANDBY NOT SELECTED READ WRITE /OE X H L X /CE H L L L /WE X H H L DQ HIGH-Z HIGH-Z Dout Din POWER STANDBY ACTIVE ACTIVE ACTIVE
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HANBit ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN,OUT VCC PD TSTG
HMS12832M4
RATING -0.5V to Vcc+0.5V -0.5V to +7.0V 4.0W -65oC to +150oC
Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.5*
( TA=0 to 70 o C )
TYP. 5.0V 0 -
MAX 5.5V 0 Vcc+0.5V** 0.8V
VIL(Min.) = -2.0V ac (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V ac (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC TA 70 oC ; Vcc = 5V 10% )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=5.0V, Temp=25 oC TEST CONDITIONS VIN=Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0mA IOL = 8.0mA SYMBO L ILI IL0 VOH VOL MIN -2 -2 2.4 0.4 MAX 2 2 UNITS A A V V
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HANBit
HMS12832M4
DC AND OPERATING CHARACTERISTICS (2)
MAX DESCRIPTION Power Supply Current:Operating Power Supply Current:Standby TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CE=VIH f=0MHZ, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V (TA =25 oC , f= 1.0Mhz) TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN MAX 8 8 UNIT pF pF SYMBOL ICC ISB ISB1 -12 75 30 5 -15 73 30 5 -20 70 30 5 UNIT mA mA mA
CAPACITANCE
DESCRIPTION Input /Output Capacitance Input Capacitance
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 5V 0.5V, unless otherwise specified)
Test conditions
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load VALUE 0V to 3V 3ns 1.5V See below
Output +5V
Load
Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5V
480 DOUT 255 30pF* DOUT 255
480 5pF*
READ CYCLE
-12 PARAMETER Read Cycle Time Address Access Time
SYMBOL
-15 MAX MIN 15 12 15 MAX MIN 20
-20
UNIT
MIN tRC tAA 12
MAX ns 20 ns
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HANBit
Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change Chip Select to Power Up Time Chip Select to Power Down Time tCO tOE tOLZ tLZ tOHZ tHZ tOH tPU tPD 0 3 0 0 3 0 12 6 6 12 6 0 3 0 0 3 0 15 7 7 15 7
HMS12832M4
20 9 0 3 0 0 3 0 20 9 9 ns ns ns ns ns ns ns ns ns
WRITE CYCLE
-12 PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z
SYMBOL MIN MAX MIN MAX MIN MAX
-15
-20
UNIT
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
12 8 0 8 8 0 0 6 0 3 6
15 10 0 9 9 0 0 7 0 3 7
20 12 0 10 10 0 0 8 0 3 9
ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(Address Controlled) ( /CE =/ OE = VIL , /WE = VIH)
tRC Address tAA tOH Data out
Previous Data Valid Data Valid
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HANBit
HMS12832M4
TIMING WAVEFORM OF READ CYCLE ( /CE Controlled )
tRC Address tAA /CE tLZ(4,5) /OE tOLZ Data Out Vcc Supply Current High-Z
Data Valid
tHZ(3,4,5) tCO tOHZ tOE tOH
lCC lSB
tPU 50%
tPD 50%
Notes (Read Cycle)
1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE=Clock )
tWC
Address
tAW tWR(5)
/OE
tCW(3)
/CE
tAS(4) tWP(2)
/WE
tDW tDH High-Z Data Valid tOHZ(6) tOW High-Z
Data In
Data Out
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HANBit
HMS12832M4
TIMING WAVEFORM OF WRITE CYCLE ( /OE Low Fixed )
tWC
Address
tAW tCW(3) tWR(5)
/CE
tAS(4) tOH tWP(2) tDW tDH Data Valid tWHZ(6,7) tOW High-Z(8) (10) (9)
/WE
Data In
High-Z
Data Out
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT l SB, l SB1 lCC lCC lCC
Note: X means Don't Care
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HANBit Electronics Co.,Ltd.
HANBit
HMS12832M4
PACKAGING INFORMATION
98.04 mm
10.16 mm 6.35 mm 16 mm
1
2.03 mm 1.02 mm 6.35 mm 6.35 mm 85.09 mm 1.27 mm
64
3.34 mm
0.25 mm MAX
2.54 mm MIN
Gold : 1.040.10 mm 1.27 Solder : 0.9140.10 mm
1.290.08 mm
(Solder & Gold Plating Lead)
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HANBit Electronics Co.,Ltd.
HANBit
HMS12832M4
ORDERING INFORMATION
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2
3
4
5
6
7
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H M S 128 32 M 4 -15
15ns Access Time HANBit Memory Modules SRAM Component SIMM x32bit 128K
1. - Product Line Identifier HANBit ------------------------------------------------------ H 2. - Memory Modules 3. - SRAM 4. - Depth : 128K 5. - Width : x 32bit 6. - Package Code SIMM ------------------------------------------------------- M 7. - Number of Memory Components 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns
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